The present invention relates to a storage system having a buffer storage, and more particularly to a storage system suitable for use when a plurality of requesters simultaneously access the buffer storage.
In a storage system having the buffer storage, the buffer storage is selected to be of smaller capacity and higher speed than a main storage, and a portion of data stored in the main storage which is most frequently used is stored in the buffer storage so that the data can be quickly accessed through the buffer storage. The buffer storage has a data area for storing the data as well as a buffer storage address area. The buffer storage address area stores addresses of the data stored in the data area and indicates whether or not the data at the accessed address is present in the data area.
Where such a buffer storage is directly accessed by a pipelined instruction processor, instruction fetch, operand fetch and operand store requests may be independently issued to the buffer storage and hence those requests may be issued simultaneously. In this case, lower priority instructions are reserved and the execution performance of the instruction processor is lowered. In order to resolve this problem, in U.S. Pat. No. 4,618,926, each of the address area and the data area of the buffer storage is divided into an instruction fetching area and an operand fetching area which are independently accessible, and an address area for only the operand store is provided.
NIKKEI ELECTRONICS, Nov. 18, 1985, pages 241 to 243 discloses a three-hierachy storage system in which an intermediate buffer storage is added between the buffer storage which is directly accessed by the instruction processor and the main storage. Usually, an input/output processor, in addition to the instruction processor, is connected to the intermediate buffer storage. Thus, access requests from those processors may be simultaneously issued. In this case, again, the lower priority access request is reserved.
A multi-processor system is disclosed in NIKKEI ELECTRONICS, Nov. 18, 1985, pages 243 and 244. A plurality of instruction processors and a plurality of input/output processors are connected to an intermediate buffer memory and hence the competition between access requests increases. In order to resolve this problem, it is proposed to provide a plurality of intermediate buffers which are independently operable in order to reduce the competition between access requests.
In those prior art systems, a plurality of buffer storages are provided to improve the system throughput. However, in those systems, the amount of hardware increases and a complex control is required to keep the contents of the plurality of buffer storages consistent.